1. Field of the Invention
The present invention relates to a data input unit of a synchronous semiconductor memory device, and more specifically, to a data input unit and a data input method of a synchronous semiconductor memory device capable of operating at a high frequency.
2. Discussion of Related Art
In order to enhance an operation speed of a DRAM, there has been developed a synchronous DRAM (Synchronous Dynamic Random Access Memory: hereinafter, referred to as “SDRAM”), which operates in synchronism with an external system clock.
In order to further enhance the data processing speed, there has been developed a Rambus DRAM and a double data rate (DDR) SDRAM which perform data processing in synchronism with a rising edge and a falling edge of one system clock.
In a DDR SDRAM, a source synchronous interface is used to transfer data at a high speed. This means that the data input/output is synchronized with a data strobe signal, commonly referred to as “DQS”, which is generated together with data from a data source.
A conventional data input unit of a synchronous semiconductor memory device is shown in FIG. 1.
The conventional data input unit comprises a DQS buffer 10 for buffering a data strobe signal DQS, a DIN buffer 20 for buffering input data DIN, a first latch 30 for latching the input data DIN in response to a rising edge dsr4 of the DQS, a second latch 40 for latching the input data DIN in response to a falling edge dsf4 of the DQS, a third latch 50 for latching the input data DIN latched in the first latch 30 in response to the falling edge dsf4 of the DQS, and a global input/output signal generator 60 for generating a global input/output signal in response to a strobe clock and the input data DIN latched in the second latch 40 and the third latch 50.
In a writing operation, a first input data is latched in the first latch 30 in response to the rising edge dsr4 of the DQS. A second input data is stored in the second latch 40 in response to the falling edge dsf4 of the DQS and, at the same time, the first input data latched in the first latch 30 is stored in the third latch 50 in response to the falling edge dsf4 of DQS.
The first and second input data latched in the third and second latches 50 and 40, respectively, are sent to the global input/output signal generator 60 in response to the strobe clock, and the global input/output signal generator 60 generates a global input/output signal GIO.
Therefore, the input data are aligned by two in response to the falling edge dsf4 of the DQS.
On the other hand, according to the JEDEC Standard, the value of a write command to first DQS latching transition (tDQSS) lies in the range of from 0.75*tCK to 1.25*tCK. Accordingly, the falling edge dsf4 of the DQS also lies in the range from 0.75*tCK to 1.25*tCK, and thus a margin of the falling edge dsf4 of the DQS is 0.5*tCK. This will be explained with reference to FIG. 2 as follows.
In FIG. 2, a data latched when the tDQSS is 0.75*tCK, a data latched when the tDQSS is 1.25*tCK, and a strobe clock are shown.
As shown in FIG. 2, an interval where valid data always exists is 1.0*tCK (a period in which the falling edge dsf4 signals of the DQS are input) −0.5*tCK (a difference between times at which the falling edge dsf4 signals of the DQS may be latched since the falling edge dsf4 signals of the DQS may be input with a time difference of 0.5*tCK)=0.5*tCK. Therefore, the maximum margin of the data which is synchronized with the strobe clock occurs when the strobe clock lies at the exact middle point of the interval where the valid data always exists, and in this case, the maximum margin is 0.25*tCK.
The ordinary operation is performed as described above. The DQS should return to a high impedance state Hi-Z after a Write DQS Postamble Time tWPST of 0.4˜0.6*tCK when the data input in the write operation is finished. However, if an additional undesirable pulse is generated due to a generation of ringing in the DQS, an erroneous write operation may occur.
When the tDQSS is 0.75*tCK, a DQS ringing generated after the tWPST of 0.4˜0.6*tCK, that is, after the second DQS, is shown in FIG. 3. The first and second input data are aligned normally in response to the normal falling edge dsf4 signal. However, when the additional rising and falling edges dsr4 and dsf4 are generated internally by a DQS glitch signal newly generated due to the DQS ringing, the third and fourth input data are changed into unknown new data in response to the additional falling edge dsf4. As a result, the unknown data are aligned in response to the additional falling edge signal dsf4 before the strobe clock signal is generated. Accordingly, erroneous global input/output signals GIO may be generated.
To prevent this error, the strobe clock signal should be applied before the additional falling edge signal dsf4 is generated, so that correct data is sent to the global input/output signal generator 60.
The interval between the strobe clock signal and the last DQS signal generated (the DQS signal when the value of tDQSS is 0.75*tCK) is 0.75*tCK. Therefore, an error will not occur if the frequency satisfies a condition of 0.75*tCK≦0.4*tCK (minimum value of tWPST, which has a range of 0.4*tCK to 0.6*tCK)+rPW (pluse width of the ringing signal, the pulse width being a time until the falling of the ringing signal occurs because the falling edge signal dsf4 is generated by the falling edge signal of the DQS). If the value of the rPW is 400 ps, the period of the clock pulse tCK should be larger than 14 ns to prevent the error.
Therefore, in the conventional circuit, the write operation may not be performed at a high frequency because the margin between the strobe clock signal and the data latched in response to the falling edge signal dsf4 is too small, and in this case, an error of the write operation may occur when the ringing signal is generated in the DQS signal.